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cy8c24633 psoc ? programmable system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-20160 rev. *g revised november 19, 2012 features powerful harvard-architecture processor ? m8c processor speeds to 24 mhz ? 8 8 multiply, 32-bit accumulate ? low power at high speed ? 3.0 to 5.25 v operating voltage ? industrial temperature range: ?40 c to +85 c advanced peripherals (psoc ? blocks) ? four rail-to-rail analog psoc blocks provide: ? up to 14-bit adcs ? up to 8-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? four digital psoc blocks provide: ? 8- to 32-bit timers and count ers, 8- and 16-bit pulse-width modulators (pwms) ? crc and prs modules ? full-duplex uart ? multiple spi masters or slaves ? connectable to all gpio pins ? complex peripherals by combining blocks ? high speed 8-bit sar adc optimized for motor control precision, programmable clocking ? internal 5% 24/48 mhz oscillator ? high accuracy 24 mhz with optional 32 khz crystal and pll ? optional external oscillator, up to 24 mhz ? internal oscillator for watchdog and sleep flexible on-chip memory ? 8k flash program storage 50,000 erase/write cycles ? 256 bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink on all gpio ? pull-up, pull-down, high z, strong, or open drain drive modes on all gpio ? up to eight analog inputs on gpio plus two additional analog inputs with restricted routing ? two 30 ma analog outputs on gpio ? configurable interrupt on all gpio additional system resources ? i 2 c slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full-featured in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128kb trace memory
cy8c24633 document number: 001-20160 rev. *g page 2 of 52 digital system sram 256 bytes interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 8k digital block array multiply accum. internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog ref analog input mu xi n g i 2 c po r t 2 po r t 1 po r t 0 analog dr iv er s system bus an alo g block array 1 row 4 blocks 2 columns 4 blocks sar8 adc po r t 3 block diagram
cy8c24633 document number: 001-20160 rev. *g page 3 of 52 contents features ............................................................................. 1 block diagram .................................................................. 2 contents ............................................................................ 3 psoc functional overview .............................................. 4 the psoc core ........................................................... 4 the digital system ...................................................... 4 the analog system ..................................................... 5 additional system resources ..................................... 6 psoc device characteristics . ..................................... 6 getting started .................................................................. 7 application notes ........................................................ 7 development kits ........................................................ 7 training ....................................................................... 7 cypros consultants .................................................... 7 solutions library .......................................................... 7 technical support ....................................................... 7 development tools .......................................................... 8 psoc designer software subsyst ems .......... .............. 8 designing with psoc designer ....................................... 9 select user modules ................................................... 9 configure user modules .............................................. 9 organize and connect .............. .............. ........... ......... 9 generate, verify, and debug ....................................... 9 pinouts ............................................................................ 10 28-pin part pinout ..................................................... 10 56-pin part pinout .............. .............. .............. ........... 11 register reference ......................................................... 12 register conventions ................................................ 12 register mapping tables ...... .............. .............. ........ 12 electrical specifications ................................................ 15 absolute maximum ratings .. .................................... 16 operating temperature ............................................ 16 dc electrical characteristics ..................................... 17 ac electrical characteristics ..................................... 30 thermal impedances ................................................ 41 capacitance on crystal pins .............. .............. ........ 41 solder reflow peak temperat ure ............................. 41 ordering information ...................................................... 42 packaging information ................................................... 43 acronyms ........................................................................ 44 acronyms used ......................................................... 44 reference documents .................................................... 44 document conventions ................................................. 45 units of measure ....................................................... 45 numeric conventions ............ .................................... 45 glossary .......................................................................... 46 document history page ................................................. 51 sales, solutions, and legal information ...................... 52 worldwide sales and design s upport ......... .............. 52 products .................................................................... 52 psoc? solutions ...................................................... 52
cy8c24633 document number: 001-20160 rev. *g page 4 of 52 psoc functional overview the psoc family consists of many programmable system-on-chip with on-chip cont roller devices. these devices are designed to replace multiple traditional mcu-based system components with one, low cost single-chip programmable device. psoc devices include configurable blocks of analog and digital logic, as well as programmable interconnects. this architecture allows the user to create customized peripheral configurations that match the re quirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the psoc architecture, as illustrated in the block diagram , is comprised of four main areas: psoc core, digital system, analog system, and system resources. configurable global buses allows all the device resources to be combined into a complete custom system. the psoc cy8c24 x33 family can have up to three i/o ports that connect to the global digital and analog interconnects, providing access to four digital blocks and four analog blocks. the psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable general purpose i/o (gpio). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard-architecture microprocessor. the cpu utilizes an interrupt controller with 11 vectors, to simplify programmi ng of real time embedded events. program execution is timed an d protected using the included sleep and watch dog timers (wdt). memory encompasses 8 kb of flash for program storage, 256 bytes of sram for data st orage, and up to 2 kb of eeprom emulated using the flash. program flash uses four protection levels on blocks of 64 bytes, allowing customized software ip protection. the psoc device incorporates flexible internal clock generators, including a 24 mhz internal main oscillator (imo) accurate to 5% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz internal low speed oscillator (ilo) is provided for the sleep timer and wdt. if crystal accuracy is desired, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24 mhz system clock using a pll. the clocks, together with progr ammable clock dividers (as a system resource), provide the flexibilit y to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing gr eat flexibility in external interfacing. every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. the digital system the digital system is composed of four digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user module references. figure 1. digital system block diagram digital peripheral configurations include those listed below. pwms (8- and 16-bit) pwms with dead band (8- and 16-bit) counters (8- to 32-bit) timers (8- to 32-bit) uart 8 bit with selectable parity (up to 1) spi master and slave (up to 1) i 2 c slave and master (1 avai lable as a system resource) cyclical redundancy checker/generator (8- to 32-bit) irda (up to 1) pseudo random sequence generators (8- to 32-bit) the digital blocks are connected to any gpio through a series of global buses that route any signal to any pin. the buses also allow signal multiplexing and performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by psoc device fa mily. this allows the optimum choice of system resources fo r your application. family resources are shown in ta b l e 1 on page 6. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect po r t 3 po r t 1 po r t 0 po r t 2
cy8c24633 document number: 001-20160 rev. *g page 5 of 52 the analog system the analog system is composed of an 8-bit sar adc and four configurable blocks. the progr ammable 8-bit sar adc is an optimized adc that runs up to 300 ksps, with monotonic guarantee. it also has the feat ures to support a motor control application. each analog block is comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific appli- cation requirements. some of the more common psoc analog functions (most available as user modules) are listed below. filters (2 and 4 pole band pass, low-pass, and notch) amplifiers (up to two, with selectable gain to 48x) instrumentation amplifiers (1 with selectable gain to 93x) comparators (up to two, with 16 selectable thresholds) dacs (up to two, with 6- to 9-bit resolution) multiplying dacs (up to 2, with 6- to 9-bit resolution) high current output drivers (two with 30 ma drive as a core resource) 1.3 v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are arranged in a co lumn of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks. the analog column 0 contains the sar8 adc block rather than the standard sc blocks. figure 2. analog system block diagram acb00 acb01 block array array input configuration aci1[1:0] aci0[1:0] p0 [ 6 ] p0 [ 4 ] p0 [ 2 ] p0 [ 0 ] p2 [ 2 ] p2 [ 0 ] p2 [ 6 ] p2 [ 4 ] refin agndin p0 [ 7 ] p0 [ 5 ] p0 [ 3 ] p0 [ 1 ] p2 [ 3 ] p2 [ 1 ] re f e r e n ce ge ne r ator s agndin ref in bandgap ref hi ref lo agnd asd11 asc21 interface to dig ital sys t e m m8c interface (address bus, data bus, etc.) analog reference 8-bit sar adc aci2[3:0] p0[7:0]
cy8c24633 document number: 001-20160 rev. *g page 6 of 52 additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems. additional resources include a multiplier, decimator, low voltage detection, and power on reset. brief statements describing the merits of each system resource are presented below. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using di gital psoc blocks as clock dividers. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma adcs. the i 2 c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low-voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced power-on reset (por) circuit eliminates the need for a system supervisor. an internal 1.3 v reference provides an absolute reference for the analog system, including adcs and dacs. psoc device characteristics depending on your psoc device characteristics, the digital and an alog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. the following tabl e lists the resources available for specific psoc device groups. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size sar adc cy8c29x66 up to 64 4 16 up to 12 4 4 12 2 k 32 k no cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [1] 1 k 16 k yes cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k no cy8c24x94 up to 56 1 4 up to 48 2 2 6 1 k 16 k no cy8c24x23a up to 24 1 4 up to 12 2 2 6 256 4 k no cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k yes cy8c22x45 up to 38 2 8 up to 38 0 4 6 [1] 1 k 16 k no cy8c21x45 up to 24 1 4 up to 24 0 4 6 [1] 512 8 k yes cy8c21x34 up to 28 1 4 up to 28 0 2 4 [1] 512 8 k no cy8c21x23 up to 16 1 4 up to 8 0 2 4 [1] 256 4 k no cy8c20x34 up to 28 0 0 up to 28 0 0 3 [1,2] 512 8 k no cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [1,2] up to 2 k up to 32 k no notes 1. limited analog functionality. 2. two analog blocks and one capsense ? .
cy8c24633 document number: 001-20160 rev. *g page 7 of 52 getting started for in depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics an d skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assis- tance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736.
cy8c24633 document number: 001-20160 rev. *g page 8 of 52 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (d acs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this lets you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also lets you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-s ensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulat ion pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation.
cy8c24633 document number: 001-20160 rev. *g page 9 of 52 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called ps oc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pwm user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width and duty cycle. configure the param- eters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifi- cations. each datasheet describes the use of each user module parameter, and other information that you may need to success- fully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development environment lets you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full-speed. psoc designer debugging capabil- ities rival those of systems cost ing many times more. in addition to traditional single-step, run-to -breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.
cy8c24633 document number: 001-20160 rev. *g page 10 of 52 pinouts the psoc cy8c24633 is available in 28-pin ssop and 56-pin ssop ocd packages. refer to the following information for details. every port pin (labeled with a ?p?), except v ss , v dd , and xres in the following tables and illustrations, is capable of digital i/o. 28-pin part pinout the 28-pin part is for the cy8c24633 psoc device. table 2. 28-pin part pinout (ssop) pin no. digital analog pin name description figure 3. cy8c24633 psoc device 1 i/o i p0[7] analog col mux ip and adc ip 2 i/o i/o p0[5] analog col mux ip and column o/p and adc ip 3 i/o i/o p0[3] analog col mux ip and column o/p and adc ip 4 i/o i p0[1] analog col mux ip and adc ip 5 i/o p2[7] gpio 6 i/o p2[5] gpio 7 i/o i p2[3] direct switched capacitor input 8 i/o i p2[1] direct switched capacitor input 9 i/o avref p3[0] [3] gpio/adc vref (optional) 10 i/o p1[7] i 2 c scl 11 i/o p1[5] i 2 c sda 12 i/o p1[3] gpio 13 i/o p1[1] [4] gpio, xtal input, i2c scl, issp scl 14 power vss ground pin 15 i/o p1[0] [4] gpio, xtal output, i2c sda, issp sda 16 i/o p1[2] gpio 17 i/o p1[4] gpio, external clock ip 18 i/o p1[6] gpio 19 xres external reset 20 i/o i p2[0] direct switched capacitor input 21 i/o i p2[2] direct switched capacitor input 22 i/o p2[4] gpio 23 i/o p2[6] gpio 24 i/o i p0[0] analog col mux ip and adc ip 25 i/o i p0[2] analog col mux ip and adc ip 26 i/o i p0[4] analog col mux ip and adc ip 27 i/o i p0[6] analog col mux ip and adc ip 28 power vdd supply voltage legend a = analog, i = input, and o = output aio, p0[7] io, p0[5] io, p0[3] aio, p0[1] io, p2[7] io, p2[5] aio, p2[3] aio, p2[1] avref, io, p3[0] i2c scl, io, p1[7] i2c sda, io, p1[5] io, p1[3] i2c scl, issp scl, xtalin, io, p1[1] vss vdd p0[6], aio, ancolmux and adc ip p0[4], aio, ancolmux and adc ip p0[2], aio, ancolmux and adc ip p0[0], aio, ancolmux and adc ip p2[6], io p2[4], io p2[2], aio p2[0], aio xres p1[6], io p1[4], io, extclk p1[2], io p1[0], io, xtalout, issp sda, i2c sda ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 notes 3. even though p3[0] is an odd port, it resides on the left side of the pinout. 4. issp pin, which is not high z at por.
cy8c24633 document number: 001-20160 rev. *g page 11 of 52 56-pin part pinout the 56-pin ocd (on-chip debug) part is for the cy8c24633 (cy8c24033) psoc device. note ocd parts are only used for in-circuit debugging . ocd parts are not available for production. table 3. 56-pin ocd part pinout (ssop) pin no. name description figure 4. cy8c24033 ocd psoc device 1 nc no internal connection 2 p0[7] analog column mux input: ai 3 p0[5] analog column mux input and column output: aio 4 p0[3] analog column mux input and column output: aio 5 p0[1] analog column mux input: ai 6 p2[7] 7 p2[5] 8 p2[3] direct switched capacitor block input: ai 9 p2[1] direct switched capacitor block input: ai 10 nc no internal connection 11 p3[0] gpio/adc vref (optional) 12 nc no internal connection 13 nc no internal connection 14 ocde ocd even data i/o 15 ocdo ocd odd data output 16 nc no internal connection 17 nc no internal connection 18 nc no internal connection 19 nc no internal connection 20 nc no internal connection 21 nc no internal connection 22 nc no internal connection 23 p1[7] i2c serial clock (scl) 24 p1[5] i2c serial data (sda) 25 nc no internal connection 26 p1[3] 27 p1[1] [5] crystal (xtalin), i2c serial clock (scl) 28 vss ground connection 29 nc no internal connection 30 nc no internal connection pin no. name description 31 p1[0] [5] crystal (xtalout), i2c serial data (sda) 44 nc no internal connection 32 p1[2] 45 nc no internal connection 33 p1[4] optional external clock input (extclk) 46 nc no internal connection 34 p1[6] 47 nc no internal connection 35 nc no internal connection 48 p2[0] direct switched capacitor block input: ai 36 nc no internal connection 49 p2[2] direct switched capacitor block input: ai 37 p3[1] gpio 50 p2[4] external analog ground (agnd) 38 nc no internal connection 51 p2[6] external voltage reference (vref) 39 nc no internal connection 52 p0[0] analog column mux input: ai 40 nc no internal connection 53 p0[2] analog column mux input and column output: aio 41 xres active high pin reset with internal pull down 54 p0[4] analog column mux input and column output: aio 42 hclk ocd high speed clock output 55 p0[6] analog column mux input: ai 43 cclk ocd cpu clock output 56 vdd supply voltage legend a = analog, i = input, o = output. ocd ssop 156 vdd 2 ai, p0[7] 55 p0[6], ai 3 aio, p0[5] 54 p0[4], aio 4 aio, p0[3] 53 p0[2], aio 5 ai, p0[1] 52 p0[0], ai 6 p2[7] 51 p2[6], external vref 7 p2[5] 50 p2[4], external agnd 8 ai, p2[3] 49 p2[2], ai 9 ai, p2[1] 48 p2[0], ai 10 47 11 gpio/adc vref, p3[0] 46 12 45 13 44 14 ocde 43 cclk 15 ocdo 42 hclk 16 41 xres 17 nc 40 nc 18 nc 39 nc 19 nc 38 nc 20 37 p 3 [ 1 ] 21 nc 36 n c 22 nc 35 nc 23 i2c scl, p1[7] 34 p1[6] 24 i2c sda, p1[5] 33 p1[4], extclk 25 nc 32 p1[2] 26 p1[3] 31 p1[0], xtalout, i2c sda, sdata 27 sclk, i2c scl, xtalin, p1[1] 30 nc 28 vss 29 nc nc nc nc nc nc nc nc nc nc nc not for production note 5. issp pin, which is not high z at por.
cy8c24633 document number: 001-20160 rev. *g page 12 of 52 register reference this section lists the registers of the cy8c24633 psoc device by using mapping tables, in offset order. register conventions the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks, bank 0 and bank 1. the xio bit in the flag register (cpu_f) determines which bank the user is currently in. when the xio bit is set to 1, the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
cy8c24633 document number: 001-20160 rev. *g page 13 of 52 table 4. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 80 c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 asd11cr0 84 rw c4 prt1ie 05 rw 45 asd11cr1 85 rw c5 prt1gs 06 rw 46 asd11cr2 86 rw c6 prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb prt3dr 0c rw 4c 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw 4e 8e ce prt3dm2 0f rw 4f 8f cf 10 50 90 d0 11 51 91 d1 12 52 92 d2 13 53 93 d3 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw i 2 c_cfg d6 rw 17 57 asc21cr3 97 rw i 2 c_scr d7 # 18 58 98 i 2 c_dr d8 rw 19 59 99 i 2 c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # saradc_dl 67 rw a7 dec_cr1 e7 rw dcb02dr0 28 # 68 a8 mul0_x e8 w dcb02dr1 29 w saradc_c0 69 # a9 mul0_y e9 w dcb02dr2 2a rw saradc_c1 6a rw aa mul0_dh ea r dcb02cr0 2b # 6b ab mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw ac acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw ad acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw ae acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw af acc0_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 * 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 * 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved. # access is bit specific.
cy8c24633 document number: 001-20160 rev. *g page 14 of 52 table 5. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 80 c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 asd11cr0 84 rw c4 prt1dm1 05 rw 45 asd11cr1 85 rw c5 prt1ic0 06 rw 46 asd11cr2 86 rw c6 prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw d6 17 57 asc21cr3 97 rw d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 saradc_trs a8 rw imo_tr e8 w dcb02in 29 rw 69 saradc_trcl a9 rw ilo_tr e9 w dcb02ou 2a rw 6a saradc_trch aa rw bdg_tr ea rw 2b 6b saradc_c2 ab # eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw saradc_lcr ac rw ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 * 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved. # access is bit specific.
cy8c24633 document number: 001-20160 rev. *g page 15 of 52 electrical specifications this section presents the dc and ac electric al specifications of the cy8c24633 psoc dev ice. for the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc . specifications are valid for ?40 o c ? t a ? 85 o c and t j ? 100 o c, except where noted. refer to table 22 for the electrical sp ecifications on the imo using slimo mode. figure 5. voltage versus cpu frequency figure 5a. imo frequency trim options 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 slimo mode=1 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0
cy8c24633 document number: 001-20160 rev. *g page 16 of 52 absolute maximum ratings operating temperature table 6. absolute maximum ratings symbol description min typ max units notes t stg storage temperature ?55 25 +100 o c higher storage temperatures reduce data retention time. recommended storage temperature is +25 o c 25 o c. extended duration storage temperatures above 65 o c degrade reliability. t baketemp bake temperature ? 125 see package label o c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on v dd relative to v ss -0.5 ? +6.0 v v io dc input voltage v ss - 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss - 0.5 ? v dd + 0.5 v i mio maximum current in to any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 7. operating temperature symbol description min typ max units notes t a ambient temperature ?40 ? +85 o c t j junction temperature ?40 ? +100 o c the temperature rise from ambient to junction is package specific. see thermal imped- ances by package on page 41. the user must limit the power consumption to comply with this requirement.
cy8c24633 document number: 001-20160 rev. *g page 17 of 52 dc electrical characteristics dc chip-level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 8. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.0 ? 5.25 v see table 18 on page 27. i dd supply current ? 5 8 ma conditions are v dd = 5.0 v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. slimo mode = 0. imo = 24 mhz. i dd3 supply current ? 3.3 6.0 ma conditions are v dd = 3.3 v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. slimo mode = 0. imo = 24 mhz. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [6] ? 3 6.5 ? a conditions are with internal slow speed oscillator, v dd = 3.3 v, ?40 o c ? t a ? 55 o c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. [6] ? 4 25 ? a conditions are with internal slow speed oscillator, v dd = 3.3 v, 55 o c < t a ? 85 o c, analog power = off. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal. [6] ? 4 7.5 ? a conditions are with properly loaded, 1 ? w max, 32.768 khz crystal. v dd = 3.3 v, ?40 o c ? t a ? 55 o c, analog power = off. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal at high temperature. [6] ? 5 26 ? a conditions are with properly loaded, 1 ? w max, 32.768 khz crystal. v dd = 3.3 v, 55 o c < t a ? 85 o c, analog power = off. v ref reference voltage (bandgap) 1.28 1.30 1.33 v trimmed for appropriate v dd . v dd > 3.0 v. note 6. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this should be compa red with devices that have similar functions enabled.
cy8c24633 document number: 001-20160 rev. *g page 18 of 52 dc gpio specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 9. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd ? 1.0 ? ? v ioh = 10 ma, v dd = 4.75 to 5.25 v (maximum 40 ma on even port pins (for example, p0[2], p1[4]), maximum 40 ma on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, v dd = 4.75 to 5.25 v (maximum 100 ma on even port pins (for example, p0[2], p1[4]), maximum 100 ma on odd port pins (for example, p0[3], p1[5])). 100 ma maximum combined ioh budget. i oh high level source current 10 ? ? ma i ol low level sink current 25 ? ? ma v il input low level ? ? 0.8 v v dd = 3.0 to 5.25. v ih input high level 2.1 ? v v dd = 3.0 to 5.25. v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c.
cy8c24633 document number: 001-20160 rev. *g page 19 of 52 dc operational amplifier specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog cont inuous time psoc blocks and the analog switched cap psoc blocks . the guaranteed specifications are measur ed in the analog continuous time psoc block. typical parameters apply to 5 v at 25 c and are for design guidance only. table 10. 5-v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.6 1.3 1.2 10 8 7.5 mv mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 ? v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 ? a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? v dd v dd - 0.5 v v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ? ? ? ? ? ? db db db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage s wing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high v dd - 0.2 v dd - 0.2 v dd - 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? 300 600 1200 2400 4600 400 800 1600 3200 6400 ? a ? a ? a ? a ? a psrr oa supply voltage rejection ratio 52 80 ? db v ss ?? vin ?? (v dd -2.25) or (v dd - 1.25 v) ?? vin ? v dd ?
cy8c24633 document number: 001-20160 rev. *g page 20 of 52 dc low power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 11. 3.3-v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset volta ge (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.65 1.32 ? 10 8 ? mv mv mv power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. tcv osoa average input offset voltage drift ? 7.0 35.0 v/c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 ? a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0.2 ? v dd ? 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, ppamp, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ? ? ? ? ? ? db db db specification is applicable at low opamp bias. for high opamp bias mode (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low v dd ? 0.2 v dd ? 0.2 v dd ? 0.2 ? ? ? ? ? ? v v v power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. v olowoa low output voltage swin g (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 ? 200 400 800 1600 3200 ? ? a ? a ? a ? a ? a ? a power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. psrr oa supply voltage rejection ratio 64 80 ? db v ss ?? v in ?? (v dd ? 2.25) or (v dd ? 1.25 v) ?? v in ? v dd table 12. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd - 1 v i slpc lpc supply current ? 10 40 ? a v oslpc lpc voltage offset ? 2.5 30 mv
cy8c24633 document number: 001-20160 rev. *g page 21 of 52 dc analog output bu ffer specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 13. 5v dc analog output buffer specifications symbol description min typ max units notes c l load capacitance ? ? 200 pf this specification applies to the external ci rcuit that is being driven by the analog output buffer. v osob input offset volta ge (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? ? v/c v cmob common-mode input voltage range 0.5 ? v dd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? w w v ohighob high output voltage swing (load = 32 ? to v dd /2) power = low power = high 0.5 x v dd + 1.1 0.5 x v dd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ? to v dd /2) power = low power = high ? ? ? ? 0.5 x v dd - 1.3 0.5 x v dd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 52 64 ? db v out > (v dd - 1.25). table 14. 3.3v dc analog output buffer specifications symbol description min typ max units notes c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? ? v/c v cmob common-mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? w w v ohighob high output voltage swing (load = 1 k ? to v dd /2) power = low power = high 0.5 x v dd + 1.0 0.5 x v dd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1 k ? to v dd /2) power = low power = high ? ? ? ? 0.5 x v dd - 1.0 0.5 x v dd - 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 52 64 ? db v out > (v dd - 1.25).
cy8c24633 document number: 001-20160 rev. *g page 22 of 52 dc analog reference specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the guaranteed specific ations are measured throu gh the analog continuous ti me psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power le vels for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. table 15. 5-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.136 v dd /2 + 1.288 v dd /2 + 1.409 v v agnd agnd v dd /2 v dd /2 ? 0.138 v dd /2 + 0.003 v dd /2 + 0.132 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.417 v dd /2 ? 1.289 v dd /2 ? 1.154 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.202 v dd /2 + 1.290 v dd /2 + 1.358 v v agnd agnd v dd /2 v dd /2 ? 0.055 v dd /2 + 0.001 v dd /2 + 0.055 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.369 v dd /2 ? 1.295 v dd /2 ? 1.218 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.211 v dd /2 + 1.292 v dd /2 + 1.357 v v agnd agnd v dd /2 v dd /2 ? 0.055 v dd /2 v dd /2 + 0.052 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.368 v dd /2 ? 1.298 v dd /2 ? 1.224 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.215 v dd /2 + 1.292 v dd /2 + 1.353 v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.033 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.368 v dd /2 ? 1.299 v dd /2 ? 1.225 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.076 p2[4] + p2[6] ? 0.021 p2[4] + p2[6] + 0.041 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.025 p2[4] ? p2[6] + 0.011 p2[4] ? p2[6] + 0.085 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.069 p2[4] + p2[6] ? 0.014 p2[4] + p2[6] + 0.043 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.029 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.052 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.072 p2[4] + p2[6] ? 0.011 p2[4] + p2[6] + 0.048 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.031 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.057 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.070 p2[4] + p2[6] ? 0.009 p2[4] + p2[6] + 0.047 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.033 p2[4] ? p2[6] + 0.001 p2[4] ? p2[6] + 0.039 v
cy8c24633 document number: 001-20160 rev. *g page 23 of 52 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.121 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 v dd /2 + 0.034 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.019 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.083 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.033 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.016 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.075 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.032 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.015 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.074 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 ? 0.001 v dd /2 + 0.032 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.014 v 0b011 refpower = high opamp bias = high v refhi ref high 3 bandgap 3.753 3.874 3.979 v v agnd agnd 2 bandgap 2.511 2.590 2.657 v v reflo ref low bandgap 1.243 1.297 1.333 v refpower = high opamp bias = low v refhi ref high 3 bandgap 3.767 3.881 3.974 v v agnd agnd 2 bandgap 2.518 2.592 2.652 v v reflo ref low bandgap 1.241 1.295 1.330 v refpower = medium opamp bias = high v refhi ref high 3 bandgap 2.771 3.885 3.979 v v agnd agnd 2 bandgap 2.521 2.593 2.649 v v reflo ref low bandgap 1.240 1.295 1.331 v refpower = medium opamp bias = low v refhi ref high 3 bandgap 3.771 3.887 3.977 v v agnd agnd 2 bandgap 2.522 2.594 2.648 v v reflo ref low bandgap 1.239 1.295 1.332 v 0b100 refpower = high opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.481 + p2[6] 2.569 + p2[6] 2.639 + p2[6] v v agnd agnd 2 bandgap 2.511 2.590 2.658 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.515 ? p2[6] 2.602 ? p2[6] 2.654 ? p2[6] v refpower = high opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.498 + p2[6] 2.579 + p2[6] 2.642 + p2[6] v v agnd agnd 2 bandgap 2.518 2.592 2.652 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.513 ? p2[6] 2.598 ? p2[6] 2.650 ? p2[6] v refpower = medium opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.504 + p2[6] 2.583 + p2[6] 2.646 + p2[6] v v agnd agnd 2 bandgap 2.521 2.592 2.650 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.513 ? p2[6] 2.596 ? p2[6] 2.649 ? p2[6] v refpower = medium opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.505 + p2[6] 2.586 + p2[6] 2.648 + p2[6] v v agnd agnd 2 bandgap 2.521 2.594 2.648 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.513 ? p2[6] 2.595 ? p2[6] 2.648 ? p2[6] v table 15. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c24633 document number: 001-20160 rev. *g page 24 of 52 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.228 p2[4] + 1.284 p2[4] + 1.332 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.358 p2[4] ? 1.293 p2[4] ? 1.226 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.236 p2[4] + 1.289 p2[4] + 1.332 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.357 p2[4] ? 1.297 p2[4] ? 1.229 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.237 p2[4] + 1.291 p2[4] + 1.337 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.356 p2[4] ? 1.299 p2[4] ? 1.232 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.237 p2[4] + 1.292 p2[4] + 1.337 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.357 p2[4] ? 1.300 p2[4] ? 1.233 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.512 2.594 2.654 v v agnd agnd bandgap 1.250 1.303 1.346 v v reflo ref low v ss v ss v ss + 0.011 v ss + 0.027 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.515 2.592 2.654 v v agnd agnd bandgap 1.253 1.301 1.340 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.02 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.518 2.593 2.651 v v agnd agnd bandgap 1.254 1.301 1.338 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.017 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.517 2.594 2.650 v v agnd agnd bandgap 1.255 1.300 1.337 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.015 v 0b111 refpower = high opamp bias = high v refhi ref high 3.2 bandgap 4.011 4.143 4.203 v v agnd agnd 1.6 bandgap 2.020 2.075 2.118 v v reflo ref low v ss v ss v ss + 0.011 v ss + 0.026 v refpower = high opamp bias = low v refhi ref high 3.2 bandgap 4.022 4.138 4.203 v v agnd agnd 1.6 bandgap 2.023 2.075 2.114 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.017 v refpower = medium opamp bias = high v refhi ref high 3.2 bandgap 4.026 4.141 4.207 v v agnd agnd 1.6 bandgap 2.024 2.075 2.114 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.015 v refpower = medium opamp bias = low v refhi ref high 3.2 bandgap 4.030 4.143 4.206 v v agnd agnd 1.6 bandgap 2.024 2.076 2.112 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.013 v table 15. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c24633 document number: 001-20160 rev. *g page 25 of 52 table 16. 3.3-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.170 v dd /2 + 1.288 v dd /2 + 1.376 v v agnd agnd v dd /2 v dd /2 ? 0.098 v dd /2 + 0.003 v dd /2 + 0.097 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.386 v dd /2 ? 1.287 v dd /2 ? 1.169 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.210 v dd /2 + 1.290 v dd /2 + 1.355 v v agnd agnd v dd /2 v dd /2 ? 0.055 v dd /2 + 0.001 v dd /2 + 0.054 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.359 v dd /2 ? 1.292 v dd /2 ? 1.214 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.198 v dd /2 + 1.292 v dd /2 + 1.368 v v agnd agnd v dd /2 v dd /2 ? 0.041 v dd /2 v dd /2 + 0.04 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.362 v dd /2 ? 1.295 v dd /2 ? 1.220 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.202 v dd /2 + 1.292 v dd /2 + 1.364 v v agnd agnd v dd /2 v dd /2 ? 0.033 v dd /2 v dd /2 + 0.030 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.364 v dd /2 ? 1.297 v dd /2 ? 1.222 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.072 p2[4] + p2[6] ? 0.017 p2[4] + p2[6] + 0.041 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.029 p2[4] ? p2[6] + 0.010 p2[4] ? p2[6] + 0.048 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.066 p2[4] + p2[6] ? 0.010 p2[4] + p2[6] + 0.043 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.024 p2[4] ? p2[6] + 0.004 p2[4] ? p2[6] + 0.034 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.007 p2[4] + p2[6] + 0.053 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.028 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.033 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.006 p2[4] + p2[6] + 0.056 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.030 p2[4] ? p2[6] p2[4] ? p2[6] + 0.032 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.102 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.040 v dd /2 + 0.001 v dd /2 + 0.039 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.020 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.082 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.031 v dd /2 v dd /2 + 0.028 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.015 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.083 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.032 v dd /2 ? 0.001 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.014 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.081 v dd ? 0.002 v dd v v agnd agnd v dd /2 v dd /2 ? 0.033 v dd /2 ? 0.001 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.013 v 0b011 all power settings not allowed at 3.3 v ??? ? ? ??
cy8c24633 document number: 001-20160 rev. *g page 26 of 52 0b100 all power settings not allowed at 3.3 v ??? ? ? ?? 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.211 p2[4] + 1.285 p2[4] + 1.348 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.354 p2[4] ? 1.290 p2[4] ? 1.197 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.209 p2[4] + 1.289 p2[4] + 1.353 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.352 p2[4] ? 1.294 p2[4] ? 1.222 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.218 p2[4] + 1.291 p2[4] + 1.351 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.351 p2[4] ? 1.296 p2[4] ? 1.224 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.215 p2[4] + 1.292 p2[4] + 1.354 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.352 p2[4] ? 1.297 p2[4] ? 1.227 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.460 2.594 2.695 v v agnd agnd bandgap 1.257 1.302 1.335 v v reflo ref low v ss v ss v ss + 0.01 v ss + 0.029 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.462 2.592 2.692 v v agnd agnd bandgap 1.256 1.301 1.332 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.017 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.473 2.593 2.682 v v agnd agnd bandgap 1.257 1.301 1.330 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.014 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.470 2.594 2.685 v v agnd agnd bandgap 1.256 1.300 1.332 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.012 v 0b111 all power settings not allowed at 3.3 v ??? ? ? ?? table 16. 3.3-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy8c24633 document number: 001-20160 rev. *g page 27 of 52 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc por and lvd specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. table 17. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k ? table 18. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v v dd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51 [7] 2.99 [8] 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v v v notes 7. always greater than 50 mv above v ppor (porlev=00) for falling supply. 8. always greater than 50 mv above v ppor (porlev=01) for falling supply.
cy8c24633 document number: 001-20160 rev. *g page 28 of 52 dc programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 19. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 3.0 3.1 3.2 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operation 3.0 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify v dd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 [9] ? ? ? erase/write cycles per block. flash ent flash endurance (total) [10] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years table 20. dc i 2 c specifications [11] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 3.0 v ?? v dd ?? 3.6 v ? ? 0.25 v dd v4.75 v ?? v dd ?? 5.25 v v ihi2c input high level 0.7 v dd ? ? v 3.0 v ?? v dd ?? 5.25 v
cy8c24633 document number: 001-20160 rev. *g page 29 of 52 sar8 adc dc specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. notes 9. the 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating wit hin one voltage range. voltag e ranges are 2.4 v to 3.0 v, 3.0 v to 3.6 v, and 4.75 v to 5.25 v. 10. a maximum of 36 x 50,000 block endurance cycles is allow ed. this can be balanc ed between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36 x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, use a temperature sensor user modu le (flashtemp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 11. all gpios meet the dc gpio v il and v ih specifications found in the dc gp io specifications sections. the i 2 c gpio pins also meet the above specs. table 21. sar8 adc dc specifications symbol description min typ max units notes v adcvref reference voltage at pin p3[0] when configured as adc reference voltage 3.0 ? 5.25 v the voltage level at p3[0] (when configured as adc reference voltage) should always be maintained to be less than chip supply voltage level on v dd pin. v adcvref < v dd . i adcvref current when p3[0] is configured as adc v ref 3 ??ma inl r-2r integral non-linearity [12] -1.2 ? +1.2 lsb the maximum lsb is over a sub-range not exceeding 1/16 of the full-scale range. dnl r-2r differential non-linearity [13] -1 ? +1 lsb output is monatonic. notes 12. at the 7f and 80 points, the maximum inl is 1.5 lsb. 13. for the 7f to 80 transition, the dnl specification is waived.
cy8c24633 document number: 001-20160 rev. *g page 30 of 52 ac electrical characteristics ac chip-level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 22. 5v and 3.3v ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 22.8 24 25.2 [14,15,16] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 5b on page 15. slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.5 6 6.5 [14,15,16] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 5b on page 15. slimo mode = 1. f cpu1 cpu frequency (5 v nominal) 0.093 24 24.6 [14,15] mhz slimo mode = 0. f cpu2 cpu frequency (3.3 v nominal) 0.093 12 12.3 [15,16] mhz slimo mode = 0. f 48m digital psoc block frequency 0 48 49.2 [14,15,17] mhz refer to the table 27 on page 36. f 24m digital psoc block frequency 0 24 24.6 [15,17] mhz f 32k1 internal low speed oscillator frequency 15 32 75 khz f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f 32k_u internal low speed oscillator untrimmed frequency 5 ? 100 khz f pll pll frequency ? 23.986 ? mhz is a multiple (x732) of crystal frequency. dc ilo internal low speed oscillator duty cycle 20 50 80 % t pllslew pll lock time 0.5 ? 10 ms t pllslewslow pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 1700 2620 ms t osacc external crystal oscillator startup to 100 ppm ? 2800 3800 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 uw maximum drive level 32.768 khz crystal. 3.0 v ? v dd ? 5.5 v, ?40 o c ? t a ? 85 o c. t xrst external reset pulse width 10 ? ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [14,16] mhz trimmed. utilizing factory trim values. f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time na ? ? ? s sr power_up power supply slew rate ? ? 250 v/ms t powerup time from end of por to cpu executing code ? 16 100 ms t jit_imo [18] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 700 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 900 ps n = 32 24 mhz imo period jitter (rms) ? 100 400 ps t jit_pll [18] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 800 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 1200 ps n = 32 24 mhz imo period jitter (rms) ? 100 700 ps notes 14. 4.75v < vdd < 5.25v. 15. accuracy derived from internal main oscillator with appropriate trim for vdd range. 16. 3.0v < vdd < 3.6v. 17. see the individual user module data sheets for information on maximum frequencies for user modules. 18. refer to cypress jitter specifications application note, understanding datasheet jitter specificat ions for cypress timing products ? an5054 for more information.
cy8c24633 document number: 001-20160 rev. *g page 31 of 52 figure 6. pll lock timing diagram figure 7. pll lock for low gain setting timing diagram figure 8. external crystal oscillator startup timing diagram 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1 32 khz f 32k2 32k select t os
cy8c24633 document number: 001-20160 rev. *g page 32 of 52 ac gpio specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c an d are for design guidance only. figure 9. gpio timing diagram table 23. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.5 to 5.25 v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.5 to 5.25 v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 to 5.25 v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 to 5.25 v, 10% - 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage
cy8c24633 document number: 001-20160 rev. *g page 33 of 52 ac operational amplifier specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth ar e based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3 v. table 24. 5v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 ? s ? s ? s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 ? s ? s ? s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz
cy8c24633 document number: 001-20160 rev. *g page 34 of 52 table 25. 3.3-v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.65 1.32 ? 10 8 ? mv mv mv power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. tcv osoa average input offset voltage drift ? 7.0 35.0 v/c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 ? a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0.2 ? v dd ? 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ? ? ? ? ? ? db db db specification is applicable at low opamp bias. for high opamp bias mode (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low v dd ? 0.2 v dd ? 0.2 v dd ? 0.2 ? ? ? ? ? ? v v v power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. v olowoa low output voltage swing (internal signals) power = low, ppamp opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 ? 200 400 800 1600 3200 ? ? a ? a ? a ? a ? a ? a power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. psrr oa supply voltage rejection ratio 64 80 ? db v ss ?? v in ?? (v dd ? 2.25) or (v dd ? 1.25 v) ?? v in ? v dd
cy8c24633 document number: 001-20160 rev. *g page 35 of 52 when bypassed by a capacitor on p2[4], the noise of the analog gr ound signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacit or. figure 10. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 11. typical opamp noise ? 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq ( khz) nv/rthz 0 0.01 0.1 1.0 10 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl
cy8c24633 document number: 001-20160 rev. *g page 36 of 52 ac low power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ac digital block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 26. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 ? s ? 50 mv overdrive comparator reference set within v reflpc . table 27. 5-v and 3.3-v ac digital block specifications function description min typ max unit notes all functions block input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz timer input clock frequency no capture, v dd ?? 4.75 v ? ? 49.2 mhz no capture, v dd < 4.75 v ? ? 24.6 mhz with capture ? ? 24.6 mhz capture pulse width 50 [19] ??ns counter input clock frequency no enable input, v dd ? 4.75 v ? ? 49.2 mhz no enable input, v dd < 4.75 v ? ? 24.6 mhz with enable input ? ? 24.6 mhz enable input pulse width 50 [19] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [19] ??ns disable mode 50 [19] ??ns input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (prs mode) input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (crc mode) input clock frequency ? ? 24.6 mhz spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz the i nput clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [19] ??ns note 19. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period).
cy8c24633 document number: 001-20160 rev. *g page 37 of 52 ac analog output buffer specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz table 27. 5-v and 3.3-v ac digital block specifications (continued) function description min typ max unit notes table 28. 5v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.5 2.5 ? s ? s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.2 2.2 ? s ? s sr rob rising slew rate (20% to 80%), 1v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s bw ob small signal bandwidth, 20 mv pp , 3db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 29. 3.3v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3.8 3.8 ? s ? s t sob falling settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 2.6 2.6 ? s ? s
cy8c24633 document number: 001-20160 rev. *g page 38 of 52 ac external clock specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. sr rob rising slew rate (20% to 80%), 1v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s bw ob small signal bandwidth, 20 mv pp , 3db bw, 100 pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100 pf load power = low power = high 200 200 ? ? ? ? khz khz table 29. 3.3v ac analog output buffer specifications (continued) symbol description min typ max units notes table 30. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? ? s table 31. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 [20] 0.093 ? 12.3 mhz f oscext frequency with cpu clock divide by 2 or greater [21] 0.186 ? 24.6 mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? ? s
cy8c24633 document number: 001-20160 rev. *g page 39 of 52 ac programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. sar8 adc ac specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. notes 20. maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 21. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this ca se, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. table 32. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 20 ? ms t write flash block write time ? 80 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns v dd ? 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 ? v dd ? 3.6 t eraseall flash erase time (bulk) ? 20 ? ms erase all blocks and protection fields at once. t program_hot flash block erase + flash block write time ? ? 200 ms 0 c ? t j ? 100 c t program_cold flash block erase + flash block write time ? ? 400 ms ?40 c ? t j ? 0 c table 33. sar8 adc ac specifications symbol description min typ max units notes freq 3 input clock frequency 3 v ? ?3.0mhz freq 5 input clock frequency 5 v ? ?3.0mhz
cy8c24633 document number: 001-20160 rev. *g page 40 of 52 ac i 2 c specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 12. definition for timing for fast-/standard-mode on the i 2 c bus table 34. ac characteristics of the i 2 c sda and scl pins for v dd > 3.0 v symbol description standard-mode fast-mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? ? s t highi2c high period of the scl clock 4.0 ?0.6 ? ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? ? s t hddati2c data hold time 0 ?0 ? ? s t sudati2c data set-up time 250 ? 100 [22] ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns table 35. ac characteristics of the i 2 c sda and scl pins for v dd ? ? 3.0 v (fast-mode not supported) symbol description standard-mode fast-mode units notes min max min max f scli2c scl clock frequency 0 100 ? ?khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? ? s t sustai2c set-up time for a repeated start condition 4.7 ? ? ? ? s t hddati2c data hold time 0 ? ? ? ? s t sudati2c data set-up time 250 ? ? ?ns t sustoi2c set-up time for stop condition 4.0 ? ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ? ? ? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? ? ?ns note 22. a fast-mode i2c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudati2c ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such device does st retch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i2 c-bus specification) before the scl line is released. i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
cy8c24633 document number: 001-20160 rev. *g page 41 of 52 thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 36. thermal impedances by package package typical ? ja [23] 28 ssop 95 o c/w 56 ssop 67 o c/w table 37. typical package capacitance on crystal pins package package capacitance 28 ssop 2.8 pf 56 ssop pin 27 0.33 pf pin 31 0.35 pf table 38. solder reflow peak temperature package maximum peak temperature time at maximum peak temperature 28 ssop 260 ? c 30 s 56 ssop 260 ? c 30 s
cy8c24633 document number: 001-20160 rev. *g page 42 of 52 ordering information the following table lists the cy8c24633 psoc device fa mily key package features and ordering codes. ordering code definitions notes 23. t j = t a + power x ? ja . 24. this part may be used for in-circuit debuggi ng. it is not available for production. table 39. cy8c24x33 psoc device family key features and ordering information package ordering code flash (kbytes) ram (bytes) temperature range digital blocks (rows of 4) analog blocks (columns of 3) digital i/o pins analog inputs analog outputs xres pin 28-pin (210 mil) ssop cy8c24633-24pvxi 8 256 ?40 ? c to +85 ? c 4 4 25 12 2 yes 28-pin (210 mil) ssop (tape and reel) cy8c24633-24pvxit 8 256 ?40 ? c to +85 ? c 4 4 25 12 2 yes 56-pin ocd ssop cy8c24033-24pvxi [24] 8 256 ?40 ? c to +85 ? c 4 4 24 12 2 yes cy package type: px = pdip pb-free sx = soic pb-free pvx = ssop pb-free lfx/lkx/lqx/ltx = qfn pb-free ax = tqfp pb-free bvx = vfbga pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress 8 c 24 xxx- sp xx thermal rating: c = commercial i = industrial e = extended
cy8c24633 document number: 001-20160 rev. *g page 43 of 52 packaging information this section illustrates the packaging sp ecifications for the cy8c24633 psoc device, along with the thermal impedances for each package, solder reflow peak temperature, and t he typical package capacitance on crystal pins. figure 13. 28-pin (210-mil) ssop figure 14. 56-pin (300-mil) ssop 51-85079 *e 51-85062 *f
cy8c24633 document number: 001-20160 rev. *g page 44 of 52 acronyms acronyms used ta b l e 4 0 lists the acronyms that are used in this document. reference documents design aids ? reading and writing psoc ? flash ? an2015 (001-40459) table 40. acronyms used in this datasheet acronym description acronym description ac alternating current mips million instructions per second adc analog-to-digital converter ocd on-chip debug api application programming interface pcb printed circuit board cpu central processing unit pga programmable gain amplifier crc cyclic redundancy check pll phase-locked loop ct continuous time por power on reset dac digital-to-analog converter ppor precision power on reset dc direct current prs pseudo-random sequence dnl differential nonlinearity psoc? programmable system-on-chip dtmf dual-tone multi-frequency pwm pulse width modulator eco external crystal oscillator rtc real time clock eeprom electrically erasable programmable read-only memory sar successive approximation gpio general purpose i/o sc switched capacitor ice in-circuit emulator slimo slow imo ide integrated development environment smp switch mode pump ilo internal low speed oscillator soic small-outline integrated circuit imo internal main oscillator spi tm serial peripheral interface inl integral nonlinearity sram static random access memory i/o input/output srom supervisory read only memory irda infrared data association ssop shrink small-outline package issp in-system serial programming uart universal asynchronous reciever / transmitter lpc low-power comparator usb universal serial bus lvd low-voltage detect wdt watchdog timer mac multiply-accumulate xres external reset mcu microcontroller unit
cy8c24633 document number: 001-20160 rev. *g page 45 of 52 document conventions units of measure ta b l e 4 1 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 41. units of measure symbol unit of measure symbol unit of measure kb 1024 bytes ms millisecond db decibels ns nanosecond c degree celsius ps picosecond pf picofarads v microvolts khz kilohertz mv millivolts mhz megahertz nv nanovolts lsb least significant bit v volts k ? kilo-ohm w microwatts a microamperes w watt ma milliamperes mm millimeter na nanoamperes mvpp millivolts peak-to-peak pa pikoamperes ppm parts per million s microsecond % percent
cy8c24633 document number: 001-20160 rev. *g page 46 of 52 glossary active high 5. a logic signal having its asserted state as the logic 1 state. 6. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are switched capacitor (sc) and continuous time (ct) blocks. these blocks c an be interconnected to provide adcs, dacs, multi-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. api (application programming interface) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements.
cy8c24633 document number: 001-20160 rev. *g page 47 of 52 compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is cont rolled by a piezoelectric crystal. typically a piezoelectric crys tal is less sensitive to ambient temperatur e than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communic ations, typically performed using a linear feedback shift register. similar calculations may be used for a va riety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows the user to analyze the operation of the system under development. a debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic bl ocks that can act as a counter, timer, serial receiver, serial transm itter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog-to-digital (adc) converter performs the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc devi ce. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volati le technology that provides users with the programmability and data storage of eproms, plus in-system erasability. non- volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it wa s later used as a simple internal bus system for building control electronics. i2c uses only two bi-directional pins, clock and data, both running at +5v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). glossary (continued)
cy8c24633 document number: 001-20160 rev. *g page 48 of 52 input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer progra m, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code exec ution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning t he device to the point in the program w here it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the mi croprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exch anges between two devices. or when devices are cascaded in width, the master device is the one that controls th e timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device. microcontroller an integrated circuit chip that is designed pr imarily for control systems and products. in addition to a cpu, a microcontroller typically include s memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a controller with a minima l quantity of chips, thus achieving ma ximal possible miniaturization. this in turn, reduces the volume and the cost of the cont roller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. the random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is one type of hardware reset. glossary (continued)
cy8c24633 document number: 001-20160 rev. *g page 49 of 52 psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage devi ce from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur on e after the other. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to anothe r. shift register a memory storage dev ice that sequentially shifts a wo rd either left or right to ou tput a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external inte rface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device allowing users to store and retrieve data at a high rate of speed. the term static is used because, after a value has been loaded into an sram cell, it remains unchanged until it is explicitly altered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or ac ted upon until the next active e dge of a clock signal. a system whose operation is synchronized by a clock signal. tri-state a function whose output can adopt three states: 0, 1, and z (hig h-impedance). the function does not drive any value in the z state and, in many respects, may be c onsidered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level analog and di gital psoc blocks. user modules also prov ide high level api (app lication programming interface) for the peripheral function. glossary (continued)
cy8c24633 document number: 001-20160 rev. *g page 50 of 52 user space the bank 0 space of the register map. the registers in this bank are more likely to be modified during normal program execution and not just during initialization. register s in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of tim e. glossary (continued)
cy8c24633 document number: 001-20160 rev. *g page 51 of 52 document history page document title: cy8c24633 psoc ? programmable-system-on-chip document number: 001-20160 rev. ecn no. orig. of change submission date description of change ** 1411003 hmt see ecn new spec. separate device from 001-14643. *a 1648723 hmt see ecn update sar adc electrical spec s. update inl, dnl, and vol specs. finetune specs. add 56 ssop package capacitance data. change title. make data sheet final. *b 2763970 poa/aesa 09/16/2009 update gettin g started, development tools, and designing with psoc designer sections. *c 2871212 jhu/hmt 02/04/2010 add table of contents . update dc gpio, ac chip-level, and ac programming specifications as follows: ? add ioh, iol. existing parameter. previous ly only in ?notes? section of voh/vol. now added as a separate line item for ease of location in data sheet. ? add flash endurance note regarding the programming and verifying flash should be in the same voltage range. added to clarify flash behavior for the customer. ? add f32k_u to clarify minimum ilo frequency out before the part boots up. ? add dcilo upon request from a few customers. ? add tpowerup, typical amount of time taken by psoc to begin executing code out of flash after powerup. added to clar ify psoc behavior at startup for customer. ? revise fimo6 limits. no impact to form, fit, function, or customer application. ? revise tramp from 0 to na. replac e tramp (time) with srpower_up to accurately define the powerup requirement. ? add srpower_up, change from no limitation to limitations based on test equip- ment ratings, to which the part will now be tested. ? add tprogram_hot of maximum time it takes to erase and program a block when die temperature is >0 ? c. added to clarify flash behavior to the customer. ? add tprogram_cold of maximum time it takes to erase and program a block over the full temperature range (?40 ? c to 85 ? c). added to clarify flash behavior to the customer. ? revise twrite to align with recommended values for third party programmers. data sheet now matches the typical value as recommended. update copyright and sales, solutions, and legal information urls. update 28-pin ssop package diagram. *d 3115813 njf 12/20/10 updated psoc device characteristics table . added dc i 2 c specifications table. added tjit_imo specification, remo ved existing jitter specifications. updated dc analog referenc e specifications and 3.3 v dc operational amplifier specifications tables. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes were made to ac di gital block specifications table and i 2 c timing diagram. they were updated for clearer understanding. updated figure 10 since the labelling for y-axis was incorrect. added ordering code definitions. *e 3284078 shob 07/29/10 updated getting started , development tools , and designing with psoc designer updated solder reflow peak temperature table. removed reference to obsolete application note an2012. *f 3598339 lure/ xzng 04/24/2012 changed the pwm description string from ?8- to 32-bit? to ?8- and 16-bit?. *g 3816133 rhph 11/19/2012 updated package diagram 51-85062 to *f removed reference to the obsolete spec 001-14503 from reference documents section.
document number: 001-20160 rev. *g revised november 19, 2012 page 52 of 52 psoc designer? is a trademark and psoc? is a registered trademark of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c24633 ? cypress semiconductor corporation, 2007-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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